1. Field of the Invention
The present invention relates generally to the display of video, and more particularly to adapting a system to changes in a display clock rate.
2. Background Art
A variety of display devices, such as digital monitors, liquid crystal display (LCD) televisions, and the like, are increasingly available at different screen sizes, resolutions, and display frequencies. It is often the case that parameters such as screen resolution and display frequency are adjusted during display of a video stream. In some cases, the display screen can be switched from a first display to a second display during the rendering of a video stream. The switching of displays, or of display characteristics such as size, resolution and frequency, can result in a change in the pixel clock frequency. The pixel clock frequency or pixel rate, as used herein, is the rate at which the images and/or video are rendered on the display screen. The pixel clock frequency depends primarily on the display characteristics of the display screen.
The data processing pipeline that prepares the images and video for display on the display screen is typically driven based upon a display clock that is, in general, synchronized to the pixel clock. The display clock rate is generally set at a rate equal to or greater than the pixel clock rate.
In many conventional systems, the display clock is set based on the highest applicable pixel clock. However, this approach may consume more power than would be required because the pixel clock can be lower than the highest applicable rate in most cases.
It may be desired that the display clock can be changed on-the-fly (i.e., during the display of images and/or video). Changes to the display clock rate may be required to support aspects, such as, switching of display screens, changing of display characteristics, and efficient power consumption. Changing the display clock to the lowest rate that can support the required pixel clock rate of the display screen(s) when possible, for example, can result in substantial reductions in source power requirements and reductions in power consumption. Such a change in the display clock changes can be affected automatically for reasons such as power saving and/or can be user-initiated. A synchronization mismatch of the display clock and the pixel clock can result in display artifacts (e.g., video corruptions) being visible, thus deteriorating the quality of the visual experience presented to the user.
When changing the display clock rate during the display of images and/or video, there may be an interval during which the display clock rate at which the display data processing pipeline is clocked and the pixel clock rate at which the display screens are clocked, are not synchronized. Display artifacts may be visible during this time interval in which the display clock and the pixel clock are not fully synchronized. Display artifacts include video distortions caused by the lack of pixels to display during an interval or the discarding of pixels due to buffer overflow.